Show:
0 / 0 General Information
Wednesday, 7 January 2026, 00:01 – Monday, 7 January 2036, 00:01
Course grading: Sum of SoC Project (max 50) and exam (max 50):
- 50p -> 1
- 60p -> 2
- 70p -> 3
- 80p -> 4
- 90p -> 5
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| 1 Exercises: Setting up the Virtual Machine in TC217 | |||
| 2 Git Primer | |||
| 3 NDA Agreement: FPGA lab access | SystemVerilog Intro | 0 / 1 | 0 / 0 |
0 / 0 Lectures
Wednesday, 14 January 2026, 14:01 – Monday, 14 January 2036, 14:01
1 points required to pass the module.
Lecture materials for the course are presented here. New slides will be added before each lecture.
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| 1 Introduction | |||
| 2 SystemVerilog | |||
0 / 1 SoC Survey
Wednesday, 14 January 2026, 00:01 – Thursday, 29 January 2026, 23:58
Late submissions are allowed until Sunday, 22 February 2026, 23:59.
Task: Summarize the contents of a GitHub repository assigned to your group. Report your findings in a 5-10 minute presentation: 2-3 Powerpoint slides are enough.
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| 1 SoC Survey | SoC Survey | 0 / 9 | 0 / 1 |
0 / 1 Introduction to SystemVerilog
Monday, 19 January 2026, 00:01 – Sunday, 8 February 2026, 23:58
Late submissions are allowed until Sunday, 22 February 2026, 23:59.
This optional exercise aims to introduce the basic design capabilities of SystemVerilog language.
- The design oriented properties of SystemVerilog language
- Combinational design
- Synchronous design
- Simple testbenches to support simulation
This exercise will not affect your grade. If you are taking SoC Verification, doing it again on this course is not required.
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| 0 Simulation environment | SystemVerilog Intro | 0 | 0 / 0 |
| 1 Combinational design with SystemVerilog | SystemVerilog Intro | 0 | 0 / 0 |
| 2 Synchronous design with SystemVerilog | SystemVerilog Intro | 0 | 0 / 0 |
| 3 Simple testbenches | SystemVerilog Intro | 0 / 9 | 0 / 1 |
| 4 State machines | SystemVerilog Intro | 0 | 0 / 0 |
| 5 Common cells | SystemVerilog Intro | 0 | 0 / 0 |
SoC Survey
0 / 1
SystemVerilog Intro
0 / 1