Design an AXI-DMA

Getting started & notes:

• Open the SoC-courses-vm and activate the SoC Design course environment by sourcing the soc_paths.sh script.
• It is also possible to use your own Linux environment, provided you can install the required tools. Check the README.md for links.
• Clone your group repository from course-gitlab:

$ git clone https://course-gitlab.tuni.fi/compce250-spring-2026/<GROUP_NUMBER>.git

• You can clone it directly in the home folder, but remember that the contents do not stay between logins on SoC-courses-vm.
• The project files have been updated to the group template repository. Merge these to your group repository:

$ git remote add course_upstream https://course-gitlab.tuni.fi/compce250-spring-2026/group_template_project.git
$ git fetch course_upstream
$ git merge course_upstream/main

Instructions

Follow the instructions in the README.md

Requirements and grading

This exercise is mandatory. To pass this exercise:

• All the automatic checks pass: 10 points
• After the automatic check is successful, your submission will be graded manually. Additional 0-10 points are granted based on the quality of your code.

The automatic check will run the following commands:

• find src/rtl -type f -name "*" -exec verible-verilog-lint {} ';'
• make verilate simv REF_MODEL=0
• git tag |grep -i ex1.[0-9]$

To ensure you get a passing grade, first check locally that your linter output is clean and simulation runs successfully before returning the exercise.

Returning

When you are ready and your code passes the Linter and Verilator checks,, create a tag ex1.N where N is the version (= number of submission) starting from 0. The latest tag following this format is used for manual inspection.

Ensure you have your Git repository up to date, and insert your clone url here.